(1) Field of the Invention
The present invention relates to a composition for a wiring, a wiring using the composition, a manufacturing method thereof, and a display using the wiring and a manufacturing method thereof.
(2) Description of the Related Art
Generally, wirings of semiconductor devices or displays are designed to transmit signals without delay and not to be easily opened.
In order to prevent the opening of wirings, it is suggested that the wirings have a multi-layered structure. However, this structure requires several etch process steps using different etchants.
In order to prevent delay or distortion of signals, materials having low resistivity such as aluminum or aluminum alloy are generally used. However, since the physical or chemical properties of the aluminum or aluminum alloy are not good, that is, the aluminum or aluminum alloy is easily oxidized and easily broken, process steps for compensating for the poor physical properties such as anodic oxidation process are required. Furthermore, there is a problem that the contact property between aluminum or aluminum alloy and ITO, e.g. when used for a transparent electrode of a liquid crystal display, is bad.
In the meantime, wirings for a liquid crystal become narrow since liquid crystal display are moving to a higher resolution. However, since the wiring should have limited resistance, the thickness of the wiring becomes larger. Therefore, the wiring gives large stress to a substrate for a liquid crystal display, and the stress becomes larger as the size of the substrate becomes larger.
In view of the above, it is an object of the present invention to provide a material or composition for wiring which has low resistivity and gives low stress to a substrate for a liquid crystal display.
It is another object of the present invention to provide a dual-layered wiring which can be easily manufactured.
Another object of the present invention is to simplify the manufacturing process of a display by using the dual-layered wiring and to improve its quality.
It is another object of the present invention to smooth the edge profile of contact holes exposing conductive layer or metal wiring.
Another object of the present invention is to prevent the consumption of a conductive layer under contact holes during formation of the contact holes.
A wiring according to the present invention has a dual-layered structure having a taper angle in the range of 20xcx9c70xc2x0 when manufactured under one etching condition. Otherwise, a wiring has an upper layer and a lower layer, wherein the upper conductive layer of the wiring has etch rate larger than that of the lower conductive layer by 70 to 100 xc3x85/sec.
When the wiring is etched by wet etch, only one etchant may be used for etching the two layers.
One of the conductive layers included in the wiring may be made of a material having a low resistivity equal to or less than 15 xcexcxcexa9cm, and the other conductive layer may be made of a pad material. A pad material means a material which can be used as a pad. The detailed description for a pad material is given in the detailed description.
An aluminum layer or an aluminum alloy layer may be used for one of the conductive layers. In the case of using an aluminum alloy layer, it is preferable that the aluminum alloy includes aluminum and both/either a transition metal and/or a rare earth metal less than 5%.
The other conductive layer may be made of MoW alloy including 0.01 to less than 20 atm % tungsten, the rest of molybdenum and inevitable impurities. It is preferable that the MoW alloy includes tungsten of 9 to 11 atm %.
When using aluminum as one of the conductive layers, an etchant for aluminum or aluminum alloy such as CH3COOH/HNO3/H3PO4/H2O can be used for etching the wiring. It is preferable that the concentration of HNO3 is 8 to 14%.
The wiring having a dual-layered structure can be used as a gate line or a data line for transmitting a scanning signal or a data signal in a display.
In a method for manufacturing the dual-layered wiring, a lower conductive layer is deposited on a substrate, and an upper conductive layer whose etch rate is larger than that of the lower conductive layer by 70 to 100 xc3x85/sec under the same etching condition is deposited on the lower conductive layer. The upper and the lower conductive layers are patterned to form a wiring under the etching condition, for example, using one etchant. When the wiring has a pad for receiving signals from outside and the lower conductive layer is made of a pad material, the portion of the upper conductive layer at the pad may be removed to expose the lower conductive layer.
Accordingly, a composition of MoW for a wiring comprises 0.01 to less than 20 atm % of tungsten, the rest of molybdenum and inevitable impurities. It is preferable to comprise 9 to 11 atm % of tungsten.
A single layer of the above composition can be also used as a wiring, because it has a resistivity in the range of 12 to 14 xcexcxcexa9m and is suitable for a pad. It is preferable that a edge slope of the wiring is formed in the range between 20-70xc2x0, more preferably 40-50xc2x0. The wiring can be used as a gate line or a data line of a display.
It is needless to say that the layer of this composition along with another conductive layer is used as an wiring.
A thin film transistor (hereafter referred to as a TFT) substrate according to the present invention includes a gate pattern including a gate pad, a gate electrode and a gate line which are made of a MoW layer including 0.01 to less than 20 atm % tungsten, the rest of molybdenum and inevitable impurities formed on a substrate. It is preferable that the MoW layer comprises 9 to 11 atm % of tungsten.
The gate pad, the gate electrode and the gate line may further include a conductive layer made of an aluminum or an aluminum alloy formed on or under the MoW layer. In this case, the conductive layer is simultaneously patterned along with the MoW layer using one etchant. In case of using aluminum alloy, the aluminum alloy includes aluminum and both/either transition metal and/or a rare earth metal less than 5%. CH3COOH/HNO3/H3PO4/H2O may be used as an etchant. It is preferable that the density of HNO3 is 8 to 14%.
The TFT substrate further includes a data pattern including a source electrode, a drain electrode and a data line of the TFT substrate. The data pattern may include a single layer made from one material selected from a chromium, a molybdenum and a MoW alloy. Otherwise, they may have a dual-layered structure which includes two layers made of either two selected from a chromium, a molybdenum and a MoW alloy or MoW and either aluminum or an aluminum alloy. When aluminum and aluminum alloy is used for an upper layer, it is desirable to remove the portion of the aluminum layer or the aluminum alloy layer at a pad.
When the data pattern includes a lower conductive layer of chromium and an upper layer of MoW, the upper and the lower layers are patterned under one etching condition.
The two layers are wet-etched using an etchant for chromium such as HNO3/(NH4)2Ce(NO3)6/H2O. It is preferable that the concentration of HNO3 is 4 to 10% and the concentration of(NH4)2Ce(NO3)6 is 10 to 15%.
A single layer of Mo or MoW may be also used the signal line of the large scale and high resolution liquid display, because the Mo or MoW layer gives less stress to a substrate made of a material such as glass than other conductive layers.
In a manufacturing method of a display according to the present invention, a photoresist pattern is formed on a insulating layer on a conductive layer or metal wiring and the photoresist pattern is used as a mask for forming contact holes in a thin portion and a thick portion of the insulating layer. At this time, it is preferable to form contact holes through two steps or three steps, in order to smooth the edge profile of contact holes and in order to prevent the consumption of the conductive layer under the contact holes.
In the two-step process, the first step is to etch the photoresist pattern and the insulating layer in part under the condition that etch rate of the photoresist pattern and the insulating layer is in the range between 1:1 to 1:1.5. At this time, the insulating layer and the portion of the conductive layer under the thin portion of the insulating layer may be slightly etched. Thereafter, second etching step is performed under the condition that etch rate of the insulating layer is larger than that of the conductive layer by equal to or more than 15 times.
In the three-step process, the first step is to etch insulating layer to expose a portion of the conductive layer under the thin portion of the insulating layer. Thereafter, a polymer layer is formed on the exposed surface. Finally, etching step is performed under the condition that the etch rate of the insulating layer is more than 15 times larger than the conductive layer. Here, the polymer layer prevents the lateral etching of the insulating layer.
The above method is applied to a structure including a first metal layer, a first insulating layer, a second metal layer and a second insulating layer, sequentially. That is, this method is applied to simultaneously forming a first contact hole exposing the second metal layer under the second insulating layer and a second contact hole exposing the first metal layer under the second and the first insulating layer.
This method is applied to forming contact holes exposing pads for receiving signals from outside of semiconductor device or display, in particular, simultaneously exposing gate pad and data pad.
Particularly, when using Mo or MoW for the conductive layer and silicon nitride for the insulating layer, it is preferable that the insulating layers are plasma dry-etched by using a gas system such as CF4+O2 in the final step in order to minimize the consumption of the conductive layer. In addition, it is preferable that plasma dry etch gas system in the first step is SF6+HCl(+He) or SF6+Cl2(+He) in order to smooth the edge profile of the contact holes.
When using CF4+O2 gas system, it is preferable that O2 is less than 4/10 with respect to CF4, in order to simultaneously expose gate pad and data pad of Mo or MoW through one etch step.
The amorphous silicon TFT may also include a doped amorphous silicon layer as well as an amorphous silicon layer, and this doped amorphous silicon layer is dry-etched using a mask of the data pattern. Here, because the data pattern of Mo or MoW is easily dry-etched, it is preferable to select a dry-etching gas system having etch rate less than 100 xc3x85/sec for MoW. Hydrogen halide and at least one selected from CF4, CHF3, CHClF2, CH3F and C2F6 is suitable for this purpose.